1. Field of the Invention
The present invention relates to a complex band-pass ΔΣ AD modulator, an AD converter circuit, and a digital radio receiver, and in particular, to a complex band-pass ΔΣ AD modulator for use in a digital radio receiver or the like, an AD converter circuit using the complex band-pass ΔΣ AD modulator, and a digital radio receiver using the AD converter circuit.
2. Description of the Related Art
Application of a band pass ΔΣ AD converter to an RF receiver circuit in a communication system such as a mobile phone and a radio LAN has been under consideration (for example, See first to fifth non-patent documents). Further, in an application used in the communication system (in particular, Low-IF receiver), the application of a complex band-pass ΔΣ AD modulator capable of suppressing an image signal generated on the inside of the modulator due to a mismatch between I path and Q path has been also under consideration since the image signal deteriorates a characteristic of the system (for example, See first to sixth non-patent documents). In the RF receiver circuit, when an AD converter circuit can be provided so as be shifted in a direction closer to an antenna, complicated functions which were conventionally realized by analog circuits can be realized by means of a digital signal processing method, then this achieves improvement of an integrity and a performance of the entire system.
In order to realize that, superior linearity, dynamic range, signal band and ability to eliminate the image signal are required for the AD converter circuit. Since the complex band-pass ΔΣ modulator is capable of suppressing the level of the image signal generated therein, any influence from the mismatch generated between the I and Q signal paths can be reduced. The ΔΣ AD modulator realizes a higher precision by means of an oversampling method and a noise shaping method. In the case of using a higher-order one-bit ΔΣ modulator to further pursue the high precision, the stability is a bottleneck, and a modulator having a higher-filter-order (and a higher-order digital filter as provided with the modulator at the next stage or the subsequent stage) and a higher oversampling rate (referred to as an OSR hereinafter) are required (for example, See seventh non-patent documents). In this case, it is necessary to increase the sampling ratio to increase the OSR. On the other hand, when a multi-bit ΔΣ AD modulator is used, a high resolution can be obtained with a low OSR, and the problem of the stability can be reduced (for example, See seventh and eighth non-patent documents).
Documents related to the present invention are as follows:
(1) Japanese patent laid-open publication No. JP-05-275972-A (referred to as a first patent document hereinafter);
(2) Japanese patent laid-open publication No. JP-11-017549-A (referred to as a second patent document hereinafter);
(3) Japanese patent laid-open publication No. JP-2000-244323-A (referred to as a third patent document hereinafter);
(4) Japanese patent laid-open publication No. JP-2002-100992-A (referred to as a fourth patent document hereinafter);
(5) K. Philips, “A 4. 4 mW 76 dB complex ΣΔADC for Bluetooth receivers”, ISSCC Digest of Technical Papers, Vol. 46, pp. 64–65, February 2003 (referred to as a first non-patent document hereinafter);
(6) F. Henkel et al., “A 1 MHz-bandwidth second-order continuous time quadrature band-pass sigma-delta modulator for low-IF radio receivers”, IEEE Journal of Solid-State Circuits, Vol. 37, pp. 1628–1635, December 2002 (referred to as a second non-patent document hereinafter);
(7) F. Esfahani et al., “A fourth order continuous-time complex sigma-delta ADC for low-IF GSM and EDGE receivers”, Symposium of VLSI Circuits, Digest of Technical Papers, pp. 75–78, June 2003 (referred to as a third non-patent document hereinafter);
(8) R. Schreier et al., “A 10–300 MHz IF-digitizing IC with 90–105 dB dynamic range and 15–333 kHz bandwidth”, IEEE Journal of Solid-State Circuits, Vol. 37, pp. 1636–1644, December 2002 (referred to as a fourth non-patent document hereinafter);
(9) T. Salo et al., “A dual-Mode 80 MHz band-pass ΔΣ modulator for a GSM/WCDMA IF-receiver”, ISSCC Digest of Technical Papers, Vol. 45, pp. 218–219, February 2002 (referred to as a fifth non-patent document hereinafter);
(10) S. A. Jantzi et al., “Quadrature band-pass ΔΣ modulator for digital radio”, IEEE Journal of Solid-State Circuits, Vol. 32, pp. 1935–1949, December 1997 (referred to as a sixth non-patent document hereinafter);
(11) S. R. Norsworthy et al. (editors), “Delta-Sigma Data Converters, -Theory, Design, and Simulation”, IEEE Press, 1997 (referred to as a seventh non-patent document hereinafter);
(12) T. Ueno et al., “A fourth-order band-pass Δ-Σ modulator using second order band-pass noise-shaping dynamic element matching”, IEEE Journal of Solid-State Circuits, Vol. 37, pp. 809–816, July 2002 (referred to as an eighth non-patent document hereinafter);
(13) T. Shui et al., “Mismatch shaping for a current-mode multibit delta-sigma DAC”, IEEE Journal of Solid-State Circuits, Vol. 34, pp. 331–338, March 1999 (referred to as a ninth non-patent document hereinafter);
(14) L. R. Carley, “A noise-shaping coder topology for 15 bit converters”, IEEE Journal of Solid-State Circuits, Vol. 24, pp. 267–273, April, 1989 (referred to as a tenth non-patent document hereinafter);
(15) E. Fogleman et al., “A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 53.8-dB peak SINAD and 105-dB peak SFDR”, IEEE Journal of Solid-State Circuits, Vol. 35, pp. 297–307, March 2000 (referred to as an eleventh non-patent document hereinafter);
(16) R. Schreier et al., “Speed vs. dynamic range trade-off in oversampling data converters”, in C. Toumazou et al. (editors), Trade-Offs in Analog Circuit Design, The Designer's Companion, Kluwer Academic Publishers, pp. 644–653, 2002 (referred to as a twelfth non-patent document hereinafter);
(17) Y. Yang et al., “A 114 dB 68 mW chopper-stabilized stereo multi-bit audio A/D converter”, ISSCC Digest of Technical Papers, Vol. 46, pp. 56–57, February 2003 (referred to as a thirteenth non-patent document hereinafter);
(18) B. Razavi, “Principles of Data Converter Design”, IEEE Press, 1995 (referred to as a fourteenth non-patent document hereinafter);
(19) A. Swaminathan, “A single-IF receiver architecture using a complex SD modulator”, Master of Engineering thesis, Carleton University, Ottawa, Ontario, Canada, 1997 (referred to as a fifteenth non-patent document hereinafter);
(20) D. B. Barkin et al., “A CMOS oversampling band-pass cascaded D/A converter with digital FIR and current-mode semi-digital filtering”, Symposium of VLSI Circuits, Digest of Technical Papers, pp. 79–82, June 2003 (referred to as a sixteenth non-patent document hereinafter);
(21) H. San et al, “A noise-shaping algorithm of multi-bit DAC non-linearities used in complex band-pass ΔΣ AD modulators”, Circuit and System Workshop at Karuizawa by the Institute of Electronics, Information and Communication Engineers in Japan, published by the Institute of Electronics, Information and Communication Engineers, in Japan, pp. 85–90, April 2003 (referred to as a seventeenth non-patent document hereinafter);
(22) H. San et al., “An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Band-pass Delta-Sigma AD Modulators”, IEEE 17th International Conference on VLSI Design, Mumbai, India, pp. 151–156, January 2004 (referred to as an eighteenth non-patent document hereinafter);
(23) H. San et al., “A noise-shaping algorithm of multi-bit DAC nonlinearities in complex band-pass ΔΣ modulators”, IEICE Transactions on Fundamentals, Vol. E87-A, No. 4, pp. 792–800, April 2004 (referred to as a nineteenth non-patent document hereinafter); and
(24) M. Miller, “Introduction to Sigma-Delta data converters”, IEEE 2003 Custom Integrated Circuits Conference, Educational Sessions, San Jose, U.S.A., September 2003 (referred to as a twentieth non-patent document hereinafter).
However, in contrast to the one-bit DA converter having a superior linearity, it is not possible for a non-linearity of an internal DA converter of a multi-bit ΔΣ AD modulator to be noise-shaped on the inside of the modulator, and this leads to disadvantageous deterioration in the precision of the entire AD converter. These problems will be described in detail below.
FIG. 2A is a block diagram showing a configuration of a band-pass ΔΣ AD modulator according to a prior art. FIG. 2B is an equivalent block diagram of the band-pass ΔΣ AD modulator of FIG. 2A.
Referring to FIG. 2A, the band-pass ΔΣ AD modulator includes a subtracter SU1, a band-pass filter BP1, an AD converter AD1, and a DA converter DA1. In FIG. 2A, Ain denotes an analog input signal, and Dout denotes a digital output signal. In the equivalent block diagram of FIG. 2B, the band-pass ΔΣ AD modulator includes the subtracter SU1, a band-pass filter TR1 having a transfer function H (z), and adders SM1 and SM2. In FIG. 2B, X (z) denotes the analog input signal, Y (z) denotes the digital output signal, E (z) denotes a quantization error of the AD converter AD1, and δ (z) denotes a non-linearity error of the DA converter DA1. A relationship between the input and output signals can be represented by the following Equations:
                                          M            ⁡                          (              z              )                                =                                                    H                ⁡                                  (                  z                  )                                                            1                +                                  H                  ⁡                                      (                    z                    )                                                                        ⁡                          [                                                X                  ⁡                                      (                    z                    )                                                  +                                                      1                                          H                      ⁡                                              (                        z                        )                                                                              ⁢                                      E                    ⁡                                          (                      z                      )                                                                      +                                                      1                                          H                      ⁡                                              (                        z                        )                                                                              ⁢                                                                          ⁢                                      δ                    ⁡                                          (                      z                      )                                                                                  ]                                      ,        and                            (        1        )                                          Y          ⁡                      (            z            )                          =                                                            H                ⁡                                  (                  z                  )                                                            1                +                                  H                  ⁡                                      (                    z                    )                                                                        ⁡                          [                                                [                                      X                    ⁡                                          (                      z                      )                                                        ]                                +                                                      1                                          H                      ⁡                                              (                        z                        )                                                                              ⁢                                      E                    ⁡                                          (                      z                      )                                                                      -                                  δ                  ⁡                                      (                    z                    )                                                              ]                                .                                    (        2        )            
A signal component S (z) and a noise component N (z) are defined as follows:
                                                                                          S                  ⁡                                      (                    z                    )                                                  ≡                                                                            H                      ⁡                                              (                        z                        )                                                                                    1                      +                                              H                        ⁡                                                  (                          z                          )                                                                                                      ⁢                                      X                    ⁡                                          (                      z                      )                                                                                  ,              and                                                                                          N                ⁡                                  (                  z                  )                                            ≡                                                                                          H                      ⁡                                              (                        z                        )                                                                                    1                      +                                              H                        ⁡                                                  (                          z                          )                                                                                                      ⁡                                      [                                                                                            1                                                      H                            ⁡                                                          (                              z                              )                                                                                                      ⁢                                                  E                          ⁡                                                      (                            z                            )                                                                                              -                                              δ                        ⁡                                                  (                          z                          )                                                                                      ]                                                  .                                                                        (        3        )            
It is clearly understood from the Equation (3) that the quantization noise E (z) of the internal AD converter AD1 is noise-shaped, however, the non-linearity error δ (z) of the DA converter DA1 is not noise-shaped and directly outputted, and this leads to that it is difficult to realize a ΔΣ AD converter of a higher precision.
In order to noise-shape the non-linearity of the internal multi-bit DA converter DA1 of the band-pass ΔΣ AD modulator, algorithms such as a dynamic element matching method (for example, See the eighth non-patent document) and an element rotation method (for example, See the ninth non-patent document) were proposed. However, those methods can only be applied to a real band-pass ΔΣ AD modulator having a single input terminal and a single output terminal, as shown in FIGS. 2A and 2B.
Next, a noise-shaping algorithm for noise-shaping a non-linearity of a conventional DA converter for use in a real modulator having a single input terminal and an output terminal using the element rotation method will be described. A first-order noise-shaping algorithm for first-order noise-shaping the non-linearities of DA converters which are provided in low-pass and high-pass modulators each having a single input terminal and a single output terminal is also used in a noise-shaping algorithm for a complex band-pass modulator.
FIG. 3 is a circuit diagram showing a configuration of a DA converter of nine-level precision segment current cell type according to the prior art. A relationship between the DA converter of segment type and a mismatch value in respective current cells will be described. In the DA converter of segment current cell type having a conventional nine-level resolution includes eight unit current cells CS0 to CS7, and a resistance R, as shown in FIG. 3. When a current applied to a k-th current cell CSk is defined as Ik (k=0, 1, 2, . . . , 7), all of the currents Ik are equal to each other in an ideal state. On the other hand, the current values of the respective current cells are different from each other due to variation in the processes upon manufacturing an IC chip. The current values of the respective current cells are represented by the following Equations:Ik≡I+ek (k=0, 1, 2, . . . , 7),I≡(I0+I1+I2+ . . . +I7)/8,ande0+e1+e2+ . . . +e7=0,
where ek in the above Equation denotes mismatch values in the current values Ik due to the above mentioned reason. When a digital input signal is m, and the current cells CS0, CS1, CS2, . . . , CSm-1 are turned on, then the output voltage from the DA converter is represented by the following Equation:Vout=mRI+δ.
The non-linearity δ of the DA converter is given by the following Equation:δ≡R(e0+e1+e2+ . . . +em-1).
An influence caused by the mismatch values e0, e1, . . . , e7 (or, equivalently, the non-linearity δ of the DA converter) on the output power spectrum of the AD converter is generated in a substantially flat shape within a signal band.
Next, a low-pass element rotation method disclosed in, for example, the twelfth non-patent document, will be described. FIG. 4A is a block diagram showing a configuration of a DA converter circuit using the low-pass element rotation method according to the prior art. FIG. 4B is an equivalent block diagram of the DA converter circuit of FIG. 4A.
The DA converter circuit shown in FIG. 4A includes a digital low-pass filter TR11 having a transfer function (1/(1−z−1), a DA converter DA2 having a non-linearity δ (z), and an analog high-pass filter TR12 having a transfer function (1−z−1), which are connected in a form of cascade. In this case, the digital low-pass filter TR11 of FIG. 4A includes an adder SM11, and a delay circuit DE11 for feeding back an output signal from the adder SM11 to the adder SM11, as shown in FIG. 4B. Further, the analog high-pass filter TR12 of FIG. 4A includes a subtracter SU11, and a delay circuit DE12 for delaying an output signal from the DA converter DA2 by a predetermined time length and thereafter outputting a delayed signal to the subtracter SU11, as shown in FIG. 4B. The respective signals C1 to C4 are represented by the following Equations:C2(z)=(1/(1−z−1)C1(z)  (4);C4(z)=(1−z−1)C3(z)  (5); andC3(z)=C2(z)+δ(z)  (6).
Therefore, the analog output C4 (z) is represented by the following Equation:C4(z)=C1(z)+(1−z−1)δ(z)  (7)
The non-linearity δ (z) of the DA converter DA2 is subjected to a first-order noise-shaping by the digital low-pass filter TR11 having a transfer function (1−z−1). Further, the following Equations can be obtained from the Equations (4), (5) and (6):C2(n+1)=C2(n)+C1(n+1)  (8);C4(n+1)=C3(n+1)−C3(n)  (9); andC3(n)=C2(n)+δ(n)  (10).
The non-linearity δ(z) of the DA converter DA2 could be noise-shaped if it was possible to replace the multi-bit DA converter DA2 on the inside of the low-pass ΔΣ AD modulator by the circuit shown in FIGS. 4A and 4B. However, it is actually impossible to realize such a circuit. For example, when the signal C1 (n) is always a positive integer of 2, the input signal C2 (n) inputted to the DA converter DA2 is infinite according to increase of a timing “n” and eventually exceeds an input range of the DA converter DA2, and this leads to that it impossible to accurately realize the DA conversion. The low-pass element rotation algorithm was proposed in order to solve the above-mentioned problems and can equivalently realize the circuit. The following is proposed for the DA converter of segment current cell type.
(A) The respective current cells are arranged in a ring shape in the DA converter of segment current cell type according to the prior art, as shown in FIG. 5.
(B) A pointer for storing a position of the turned-on current cell is provided in the DA converter circuit. When the pointer is set to P (n) at the timing “n”, the P (n)-th current cell is selected for the input data at a next sampling timing “n+1”.
When it is assumed that the number of the current cells is infinite, and also the following Equations are assumed:C2(n)=a,andC1(n+1)=b(0≦b≦8),
then the current cells CS0, CS1, . . . , CS (a+b−1) of the DA converter DA2 are turned on. In this case, the following Equations are obtained from the Equations (8) and (10):C3(n+1)=(a+b)RI+R(e0+e1+e2+ . . . +ea+b−1).
Further, because of the following Equation:C3(n)=aRI+R(e0+e1+e2+ . . . +ea−1),the analog signal C4(n+1) of the DA converter DA2 is represented by the following Equation:C4(n+1)=C3(n+1)−C3(n)=bRI+R(ea−1+ea+ea+1+ . . . +ea+b−1).
Concretely speaking, the current cells CS (a−1), CSa, CS (a+1), . . . , CS (a+b−1) of the DA converter are turned on. In the present example, there is a possibility that a+b−1>7. However, since the actual DA converter is provided with only eight current cells, the current cells CS (mod8(a−1)), CS (mod8 (a)), CS (mod8 (a+1)), . . . , CS (mod8 (a+b−1)) as arranged in a ring shape are turned in the case of applying the low-pass element rotation algorithm. In this specification, in place of a general notation “x modulo y” or “x mod y”, which show a remainder as obtained when “x” is divided by “y”, a simplified notation thereof, “modyx” is used for the description. An operation of the low-pass element rotation algorithm will be described in detail as follows:
(a) It is assumed that the input data is C1(n)=cn (n=0, 1, 2, 3, . . . ) at the timing “n”;
(b) The number “cn” of current cells CS (mod8 (P(n)+1)), CS (mod8 (P(n)+2)), CS (mod8 (P(n)+3)), . . . , mod8 (P(n)+cn) are turned on; and
(c) At the timing “n+1”, the pointer P (n+1) is set as follows:P(n+1)=mod8 (P(n)+cn).
FIG. 6 shows current cells (hatched parts) which are turned on when the input data changes as 4, 3, 2, 2, 5, . . . in the case of noise-shaping a non-linearity of 3-bit segment type DA converter using the low-pass noise-shaping element rotation method according to the prior art.
Referring to FIG. 6, when the input signal is “4” at the timing “n”, the current cells CS0, CS1, CS2 and CS3 are turned on. Next, when the input signal is “3” at the timing “n+1”, the current cells CS4, CS5 and CS6 are turned on. When the input signal is “2” at a timing “n+2”, the current cells CS7 and CS0(=mod8 (8)) are turned on. Further, when the input signal is “2” at a timing “n+3”, the current cells CS1 (=mod8 (9)) and CS2 (=mod8 (10)) are turned on in a manner similar to that of above. When the current cells which were turned on are thus selected clockwise, the mismatch in the current cells (that is the non-linearity of the DA converter) is subjected to the first-order noise-shaping (for example, See the eleventh to thirteenth non-patent documents) . The inventors of the present invention carried out simulations using a software of MATLAB (registered trademark), and it was confirmed that a power spectrum of the non-linearity of the DA converter was shown in the flat shape in the signal band when the conventional DA converter of segment type was used, however, the non-linearity was first-order-noise-shaped in the case of using the above-mentioned algorithm.
Next, a high-pass element rotation method as disclosed in, for example, the ninth non-patent document, will be described below. FIG. 7A is a block diagram showing a configuration of a DA converter circuit using the high-pass element rotation method according to the prior art. FIG. 7B is an equivalent block diagram of the DA converter circuit of FIG. 7A.
The DA converter circuit shown in FIG. 7A includes a digital high-pass filter TR21 having a transfer function (1/(1+z−1)), a DA converter DA3 having a non-linearity δ(z), and an analog low-pass filter TR22 having a transfer function (1−z−1), which are connected in a form of cascade. The digital high-pass filter TR21 of FIG. 7A includes a subtracter SR21, and a delay circuit DE21 for feeding back an output signal from the subtracter SR21 to the subtracter SU21, as shown in FIG. 7B. The analog low-pass filter TR22 of FIG. 7A includes an adder SM21, and a delay circuit DE22 for delaying an output signal from the DA converter DA3 by a predetermined time length and thereafter outputting a delayed output signal to the adder SM21, as shown in FIG. 7B. A relationship among respective signals D1 to D4 is represented by the following Equations:D2(z)=(1/1+z−1)D1(z)  (11),D4(z)=(1/1+z−1)D3(z)  (12),andD3(z)=D2(z)+δ(z)  (13).
Therefore, the analog output signal D4 (z) is represented by the following Equation:D4(z)=D1(z)+(1+z−1)δ(z).
The non-linearity δ(z) of the DA converter DA3 is subjected to the first-order noise-shaping by the analog low-pass filter TR22 having a transfer function (1+z−1). Further, the following Equations are obtained from the Equations (11), (12) and (13):D2(n+1)=D2(n)−D1(n+1)  (15);D4(n+1)=D3(n+1)+D3(n)  (16);andD3(n)=D2(n)+δ(z)  (17).
If it was possible to replace the multi-bit DA converter on the inside of the high-pass ΔΣ AD modulator by the circuit shown in FIGS. 7A and 7B, the non-linearity of the DA converter could be noise-shaped, however, such a circuit cannot be realized in a manner similar to that of the low-pass ΔΣ AD modulator. Accordingly, the high-pass element rotation algorithm was proposed and can equivalently realize the circuit. It is assumed that the current cells are arranged in the ring shape and the pointer is provided in the DA converter of segment current cell type. An operation of the high-pass element rotation algorithm will be described in detail as follows:
(a) At a timing “2n”:
(a1) The input data is D1 (2n)=d2n.
(a2) The number “d2n” of current cells CS (P(2n)), CS (mod8 (P(2n)+1)), CS (mod8 (P(2n)+2)), . . . , CS (mod8 (P(2n)+d2n−1)) are turned on. Concretely speaking, the number “d2n” of current cells are turned on starting from the P(2n)-th current cell and shifting in the clockwise direction.
(a3) The pointer at a timing “2n+1” is set to P(2n+1)=mod8 (P(2n)+d2n−1).
(b) At the timing “2n+1”:
(b1) The input data is D1 (2n+1)=d2n+1.
(b2) The number “d2n+1” of current cells CS (P(2n+1)), CS (mod8 (P(2n+1)−1)), CS (mod8 (P(2n+1)−2)), . . . , CS (mod8 (P(2n+1)−d2n+1)) are turned on. Concretely speaking, the number “d2n+1” of current cells are turned on, starting from the P(2n+1)-th current cell and shifting in the counterclockwise direction.
(b3) The pointer P(2n+2) at a timing “(2n+2)” is set as follows:P(2n+2)=mod8 (P(2n+1)−d2n+1+1).
FIG. 8 shows the current cells which are turned on when the input data changes as 4, 3, 2, 6, 5, . . . in the case of noise-shaping the non-linearity of the DA converter of 3-bit segment type using the high-pass noise-shaping element rotation method according to the prior art.
Referring to FIG. 8, when the input data is “4” at the timing “n”, the current cells CS0, CS1, CS2 and CS3 are turned on. Next, when the input data is “3” at the timing “n+1”, the current cells CS3, CS2” and CS1 are turned on. When the input data is “2” at the timing “n+2”, the current cells CS1 and CS2 are turned on. Further, when the input data is “6” at the timing “n+3”, the current cells CS2, CS1, CS0, CS7, CS6 and CS5 are turned on in a manner similar to that of above. More concretely, the direction in which the current cells are turned on is alternately changed between the clockwise and counterclockwise directions every time when the sampling timing changes.
As mentioned above, the input and output relationship in the band-pass ΔΣ AD modulator having the configuration of FIGS. 2A and 2B is represented by the Equation (2). It is understood from the Equation (2) that the quantization noise E (z) of the internal AD converter is noise-shaped, however, the non-linearity error δ(z) of the DA converter DA3 is not subjected to the noise shaping and directly outputted, and this leads to that it is difficult to realize the ΔΣ AD converter achieving a higher precision. More concretely, the DA converter of multi-bit type includes the non-linearity resulting from a matching precision generated in the device, which adversely affects the performance of the entire AD converter circuit. In particular, there is caused an even more serious problem when a refining process is adopted in order to downsize and accelerate the circuit. Although the AD converter circuit using the complex band-pass ΔΣ modulator was proposed in the first to fourth patent documents, the proposed AD converter circuit can not solve any mentioned problems.